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PCA9554A scps127e ? september 2006 ? revised june 2014 PCA9554A remote 8-bit i 2 c and smbus i/o expander with interrupt output and configuration registers 1 features 2 description this 8-bit i/o expander for the two-line bidirectional 1 ? i 2 c to parallel port expander bus (i 2 c) is designed for 2.3-v to 5.5-v v cc ? open-drain active-low interrupt output operation. it provides general-purpose remote i/o ? operating power-supply voltage range of 2.3 v expansion for most microcontroller families via the i 2 c to 5.5 v interface [serial clock (scl), serial data (sda)]. ? 5-v tolerant i/os the PCA9554A consists of one 8-bit configuration ? 400-khz fast i 2 c bus (input or output selection), input, output, and polarity inversion (active high or active low) registers. at ? three hardware address pins allow up to eight power on, the i/os are configured as inputs with a devices on the i 2 c/smbus weak pullup to v cc . however, the system master can ? input/output configuration register enable the i/os as either inputs or outputs by writing ? polarity inversion register to the i/o configuration bits. the data for each input or output is kept in the corresponding input or output ? internal power-on reset register. the polarity of the input port register can be ? power-up with all channels configured as inputs inverted with the polarity inversion register. all ? no glitch on power up registers can be read by the system master. ? latched outputs with high-current drive the system master can reset the PCA9554A in the maximum capability for directly driving leds event of a timeout or other improper operation by ? latch-up performance exceeds 100 ma per utilizing the power-on reset feature, which puts the registers in their default state and initializes the jesd 78, class ii i 2 c/smbus state machine. ? esd protection exceeds jesd 22 the PCA9554A open-drain interrupt ( int) output is ? 2000-v human-body model (a114-a) activated when any input state differs from its ? 200-v machine model (a115-a) corresponding input port register state and is used to ? 1000-v charged-device model (c101) indicate to the system master that an input state has changed. device information (1) part number package body size (nom) ssop (16) 6.20 mm 5.30 mm PCA9554A vqfn (16) 4.00 mm 4.00 mm qfn (16) 3.00 mm 3.00 mm (1) for all available packages, see the orderable addendum at the end of the datasheet. 1 an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. db, dbq, dgv , dw , or pw p ackage (t op view) 12 3 4 5 6 7 8 1615 14 13 12 11 10 9 a0a1 a2 p0 p1 p2 p3 gnd v cc sdascl int p7p6 p5 p4 rgv p ackage (t op view) 16 6 8 2 10 p7 p5 v cc 4 3 1 7 5 12 11 9 13 14 15 sda a0 a1 p6 int scl p3 gnd p4 a2 p0p1 p2 rgt p ackage (t op view) 16 6 8 2 10 p7 p5 v cc 4 3 1 7 5 12 11 9 13 14 15 sda a0 a1 p6 int scl p3 gnd p4 a2 p0p1 p2 productfolder sample &buy technical documents tools & software support &community
PCA9554A scps127e ? september 2006 ? revised june 2014 www.ti.com table of contents 1 features .................................................................. 1 8 detailed description ............................................ 13 8.1 functional block diagram ....................................... 13 2 description ............................................................. 1 8.2 device functional modes ........................................ 14 3 revision history ..................................................... 2 8.3 programming ........................................................... 15 4 description (continued) ........................................ 3 9 application and implementation ........................ 21 5 pin configuration and functions ........................ 3 9.1 typical application ................................................. 21 6 specifications ......................................................... 4 10 power supply recommendations ..................... 23 6.1 absolute maximum ratings ..................................... 4 10.1 power-on reset errata ......................................... 23 6.2 handling ratings ....................................................... 4 11 device and documentation support ................. 23 6.3 recommended operating conditions ....................... 4 11.1 trademarks ........................................................... 23 6.4 electrical characteristics ........................................... 5 11.2 electrostatic discharge caution ............................ 23 6.5 i 2 c interface timing requirements ........................... 6 11.3 glossary ................................................................ 23 6.6 switching characteristics .......................................... 6 12 mechanical, packaging, and orderable 6.7 typical characteristics .............................................. 7 information ........................................................... 23 7 parameter measurement information ................ 10 3 revision history changes from revision d (august 2008) to revision e page ? added interrupt errata section. ............................................................................................................................................ 15 ? added power-on reset errata section. .............................................................................................................................. 23 2 submit documentation feedback copyright ? 2006 ? 2014, texas instruments incorporated product folder links: PCA9554A
PCA9554A www.ti.com scps127e ? september 2006 ? revised june 2014 4 description (continued) int can be connected to the interrupt input of a microcontroller. by sending an interrupt signal on this line, the remote i/o can inform the microcontroller if there is incoming data on its ports without having to communicate via the i 2 c bus. thus, the PCA9554A can remain a simple slave device. the device ' s outputs (latched) have high-current drive capability for directly driving leds and low current consumption. three hardware pins (a0, a1, and a2) are used to program and vary the fixed i 2 c address and allow up to eight devices to share the same i 2 c bus or smbus. the PCA9554A is pin-to-pin and i 2 c address compatible with the pcf8574a. however, software changes are required, due to the enhancements in the PCA9554A over the pcf8574a. the PCA9554A and pca9554 are identical except for their fixed i 2 c address. this allows for up to 16 of these devices (8 of each) on the same i 2 c/smbus. 5 pin configuration and functions pin functions pin qsop (dbq) soic (dw), description qfn (rgt and name ssop (db), rgv) tssop (pw), and tvsop (dgv) a0 1 15 address input. connect directly to v cc or ground. a1 2 16 address input. connect directly to v cc or ground. a2 3 1 address input. connect directly to v cc or ground. p0 4 2 p-port input/output. push-pull design structure. p1 5 3 p-port input/output. push-pull design structure. p2 6 4 p-port input/output. push-pull design structure. p3 7 5 p-port input/output. push-pull design structure. gnd 8 6 ground p4 9 7 p-port input/output. push-pull design structure. p5 10 8 p-port input/output. push-pull design structure. p6 11 9 p-port input/output. push-pull design structure. p7 12 10 p-port input/output. push-pull design structure. int 13 11 interrupt output. connect to v cc through a pullup resistor. scl 14 12 serial clock bus. connect to v cc through a pullup resistor. sda 15 13 serial data bus. connect to v cc through a pullup resistor. v cc 16 14 supply voltage copyright ? 2006 ? 2014, texas instruments incorporated submit documentation feedback 3 product folder links: PCA9554A db, dbq, dgv , dw , or pw p ackage (t op view) 12 3 4 5 6 7 8 1615 14 13 12 11 10 9 a0a1 a2 p0 p1 p2 p3 gnd v cc sdascl int p7p6 p5 p4 rgv p ackage (t op view) 16 6 8 2 10 p7 p5 v cc 4 3 1 7 5 12 11 9 13 14 15 sda a0 a1 p6 int scl p3 gnd p4 a2 p0p1 p2 rgt p ackage (t op view) 16 6 8 2 10 p7 p5 v cc 4 3 1 7 5 12 11 9 13 14 15 sda a0 a1 p6 int scl p3 gnd p4 a2 p0p1 p2
PCA9554A scps127e ? september 2006 ? revised june 2014 www.ti.com 6 specifications 6.1 absolute maximum ratings (1) over operating free-air temperature range (unless otherwise noted) min max unit v cc supply voltage range ? 0.5 6 v v i input voltage range (2) ? 0.5 6 v v o output voltage range (2) ? 0.5 6 v i ik input clamp current v i < 0 ? 20 ma i ok output clamp current v o < 0 ? 20 ma i iok input/output clamp current v o < 0 or v o > v cc 20 ma i ol continuous output low current v o = 0 to v cc 50 ma i oh continuous output high current v o = 0 to v cc ? 50 ma continuous current through gnd ? 250 i cc ma continuous current through v cc 160 db package 82 dbq package 90 dgv package 120 ja package thermal impedance (3) dw package 57 c/w pw package 108 rgt package tbd rgv package 51 (1) stresses beyond those listed under " absolute maximum ratings " may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under " recommended operating conditions " is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) the input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. (3) the package thermal impedance is calculated in accordance with jesd 51-7. 6.2 handling ratings min max unit t stg storage temperature range ? 65 150 c human body model (hbm), per ansi/esda/jedec js-001, all 0 2000 pins (1) v (esd) electrostatic discharge v charged device model (cdm), per jedec specification 0 1000 jesd22-c101, all pins (2) (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 6.3 recommended operating conditions min max unit v cc supply voltage 2.3 5.5 v 0.7 scl, sda 5.5 v cc v ih high-level input voltage v a2 ? a0, p7 ? p0 2 5.5 scl, sda ? 0.5 0.3 v cc v il low-level input voltage v a2 ? a0, p7 ? p0 ? 0.5 0.8 i oh high-level output current p7 ? p0 ? 10 ma i ol low-level output current p7 ? p0 25 ma t a operating free-air temperature ? 40 85 c 4 submit documentation feedback copyright ? 2006 ? 2014, texas instruments incorporated product folder links: PCA9554A
PCA9554A www.ti.com scps127e ? september 2006 ? revised june 2014 6.4 electrical characteristics over operating free-air temperature range (unless otherwise noted) parameter test conditions v cc min typ (1) max unit v ik input diode clamp voltage i i = ? 18 ma 2.3 v to 5.5 v ? 1.2 v v por power-on reset voltage v i = v cc or gnd, i o = 0 v por 1.5 1.65 v 2.3 v 1.8 3 v 2.6 i oh = ? 8 ma 4.5 v 3.1 4.75 v 4.1 v oh p-port high-level output voltage (2) v 2.3 v 1.7 3 v 2.5 i oh = ? 10 ma 4.5 v 3 4.75 v 4 sda v ol = 0.4 v 2.3 v to 5.5 v 3 8 2.3 v 8 10 3 v 8 14 v ol = 0.5 v 4.5 v 8 17 4.75 v 8 35 i ol p port (3) ma 2.3 v 10 13 3 v 10 19 v ol = 0.7 v 4.5 v 10 24 4.75 v 10 45 int v ol = 0.4 v 2.3 v to 5.5 v 3 10 scl, sda 1 i i v i = v cc or gnd 2.3 v to 5.5 v a a2 ? a0 1 i ih p port v i = v cc 2.3 v to 5.5 v 1 a i il p port v i = gnd 2.3 v to 5.5 v ? 100 a 5.5 v 104 175 v i = v cc , i o = 0, i/o = inputs, 3.6 v 50 90 f scl = 400 khz, no load 2.7 v 20 65 operating mode 5.5 v 60 150 v i = v cc , i o = 0, i/o = inputs, 3.6 v 15 40 f scl = 100 khz, no load 2.7 v 8 20 i cc a 5.5 v 450 700 v i = gnd, i o = 0, i/o = inputs, 3.6 v 300 600 f scl = 0 khz, no load 2.7 v 225 500 standby mode 5.5 v 0.25 1 v i = v cc , i o = 0, i/o = inputs, 3.6 v 0.2 0.9 f scl = 0 khz, no load 2.7 v 0.1 0.8 one input at v cc ? 0.6 v, 2.3 v to 5.5 v 1.5 other inputs at v cc or gnd additional current in standby i cc ma mode every led i/o at v i = 4.3 v; 5.5 v 1 f scl = 0 khz c i scl v i = v cc or gnd 2.3 v to 5.5 v 4 5 pf sda 5.5 6.5 c io v io = v cc or gnd 2.3 v to 5.5 v pf p port 8 9.5 (1) all typical values are at nominal supply voltage (2.5-v, 3.3-v, or 5-v v cc ) and t a = 25 c. (2) the total current sourced by all i/os must be limited to 85 ma. (3) each i/o must be externally limited to a maximum of 25 ma, and the p port (p0 to p7) must be limited to a maximum current of 200 ma. copyright ? 2006 ? 2014, texas instruments incorporated submit documentation feedback 5 product folder links: PCA9554A
PCA9554A scps127e ? september 2006 ? revised june 2014 www.ti.com 6.5 i 2 c interface timing requirements over operating free-air temperature range (unless otherwise noted) (see figure 14 ) standard mode fast mode i 2 c bus i 2 c bus unit min max min max f scl i 2 c clock frequency 0 100 0 400 khz t sch i 2 c clock high time 4 0.6 s t scl i 2 c clock low time 4.7 1.3 s t sp i 2 c spike time 50 50 ns t sds i 2 c serial-data setup time 250 100 ns t sdh i 2 c serial-data hold time 0 0 ns t icr i 2 c input rise time 1000 20 + 0.1c b (1) 300 ns t icf i 2 c input fall time 300 20 + 0.1c b (1) 300 ns t ocf i 2 c output fall time 10-pf to 400-pf bus 300 20 + 0.1c b (1) 300 ns t buf i 2 c bus free time between stop and start 4.7 1.3 s t sts i 2 c start or repeated start condition setup 4.7 0.6 s t sth i 2 c start or repeated start condition hold 4 0.6 s t sps i 2 c stop condition setup 4 0.6 s t vd(data) valid data time scl low to sda output valid 300 50 ns ack signal from scl low to t vd(ack) valid data time of ack condition 0.3 3.45 0.1 0.9 s sda (out) low c b i 2 c bus capacitive load 400 400 ns (1) c b = total capacitive load of one bus in pf 6.6 switching characteristics over operating free-air temperature range (unless otherwise noted) (see figure 15 and figure 16 ) standard mode fast mode from to i 2 c bus i 2 c bus parameter unit (input) (output) min max min max t iv interrupt valid time p port int 4 4 s t ir interrupt reset delay time scl int 4 4 s t pv output data valid scl p7 ? p0 200 200 ns t ps input data setup time p port scl 100 100 ns t ph input data hold time p port scl 1 1 s 6 submit documentation feedback copyright ? 2006 ? 2014, texas instruments incorporated product folder links: PCA9554A
PCA9554A www.ti.com scps127e ? september 2006 ? revised june 2014 6.7 typical characteristics figure 1. supply current vs temperature figure 2. quiescent supply current vs temperature figure 4. supply current vs number of i/os held low figure 3. supply current vs supply voltage figure 6. i/o sink current vs output low voltage figure 5. i/o output low voltage vs temperature copyright ? 2006 ? 2014, texas instruments incorporated submit documentation feedback 7 product folder links: PCA9554A 0 5 10 15 20 25 30 35 40 45 50 55 -40 -15 10 35 60 85 t a C free-air temperature C c i cc C supply current C a v cc = 2.5 v v cc = 3.3 v v cc = 5 v f scl = 400 khz i/os unloaded 0 5 10 15 20 25 30 35 -40 -15 10 35 60 85 t a C free-air temperature C c i cc C supply current C na v cc = 2.5 v v cc = 3.3 v v cc = 5 v scl = v cc 0 25 50 75 100 125 150 175 200 225 250 275 300 -40 -15 10 35 60 85 t a C free-air temperature C c v ol C output low voltage C mv v cc = 5 v, i sink = 10 ma v cc = 2.5 v, i sink = 10 ma v cc = 2.5 v, i sink = 1 ma v cc = 5 v, i sink = 1 ma 0 5 10 15 20 25 30 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 v ol C output low voltage C v i sink C i/o sink current C ma t a = C40c v cc = 2.5 v t a = 25c t a = 85c 0 10 20 30 40 50 60 70 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 v cc C supply voltage C v i cc C supply current C a f scl = 400 khz i/os unloaded 0 50 100 150 200 250 300 350 400 450 500 550 600 0 1 2 3 4 5 6 7 8 number of i/os held low i cc C supply current C a t a = C40c v cc = 5 v t a = 25c t a = 85c
PCA9554A scps127e ? september 2006 ? revised june 2014 www.ti.com typical characteristics (continued) figure 7. i/o sink current vs output low voltage figure 8. i/o sink current vs output low voltage figure 10. i/o source current vs output high voltage figure 9. i/o output high voltage vs temperature figure 11. i/o source current vs output high voltage figure 12. i/o source current vs output high voltage 8 submit documentation feedback copyright ? 2006 ? 2014, texas instruments incorporated product folder links: PCA9554A 0 5 10 15 20 25 30 35 40 45 50 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 (v cc C v oh ) C output high voltage C v i source C i/o source current C ma t a = C40c v cc = 3.3 v t a = 25c t a = 85c 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 (v cc C v oh ) C output high voltage C v i source C i/o source current C ma t a = C40c v cc = 5 v t a = 25c t a = 85c 0 25 50 75 100 125 150 175 200 225 250 275 -40 -15 10 35 60 85 t a C free-air temperature C c (v cc C v oh ) C output high voltage C mv v cc = 5 v, i ol = 10 ma v cc = 2.5 v, i ol = 10 ma v cc = 5 v, i ol = 1 ma v cc = 2.5 v, i ol = 1 ma 0 5 10 15 20 25 30 35 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 (v cc C v oh ) C output high voltage C v i source C i/o source current C ma t a = C40c v cc = 2.5 v t a = 25c t a = 85c 0 5 10 15 20 25 30 35 40 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 v ol C output low voltage C v i sink C i/o sink current C ma t a = C40c v cc = 3.3 v t a = 25c t a = 85c 0 5 10 15 20 25 30 35 40 45 50 55 60 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 v ol C output low voltage C v i sink C i/o sink current C ma t a = C40c v cc = 5 v t a = 25c t a = 85c
PCA9554A www.ti.com scps127e ? september 2006 ? revised june 2014 typical characteristics (continued) figure 13. output high voltage vs supply voltage copyright ? 2006 ? 2014, texas instruments incorporated submit documentation feedback 9 product folder links: PCA9554A 0 1 2 3 4 5 6 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 v cc C supply voltage C v v oh C output high voltage C v i oh = C10 ma i oh = C8 ma t a = 25c
PCA9554A scps127e ? september 2006 ? revised june 2014 www.ti.com 7 parameter measurement information a. c l includes probe and jig capacitance. b. all inputs are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 ? , t r /t f 30 ns. c. all parameters and waveforms are not applicable to all devices. figure 14. i 2 c interface load circuit and voltage waveforms 10 submit documentation feedback copyright ? 2006 ? 2014, texas instruments incorporated product folder links: PCA9554A r l = 1 k w v cc c l = 50 pf (see note a) t buf t icr t sth t sds t sdh t icf t icr t scl t sch t sts t phl t plh 0.3 v cc stop condition t sps repeat start condition start orrepeat start condition scl sda start condition (s) address bit 7 (msb) data bit 10 (lsb) stop condition (p) three bytes for complete device programming sda load configura tion volt age w aveforms t icf stop condition (p) t sp dut sda 0.7 v cc 0.3 v cc 0.7 v cc r/w bit 0 (lsb) ack (a) data bit 07 (msb) address bit 1 address bit 6 byte description 1 i 2 c address 2, 3 p-port data
PCA9554A www.ti.com scps127e ? september 2006 ? revised june 2014 parameter measurement information (continued) a. c l includes probe and jig capacitance. b. all inputs are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 ? , t r /t f 30 ns. c. all parameters and waveforms are not applicable to all devices. figure 15. interrupt load circuit and voltage waveforms copyright ? 2006 ? 2014, texas instruments incorporated submit documentation feedback 11 product folder links: PCA9554A a a a a s 0 1 1 1 a1 a2 a0 1 data 1 1 p data 2 start condition 8 bits (one data bytes) from port data from port slave address r/w 8 7 6 5 4 3 2 1 t ir t ir t sps t iv address data 1 data 2 int data into port b b a a p n int r/w a t ir 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc int scl v iew b?b v iew a?a t iv r l = 4.7 k v cc c l = 100 pf (see note a) interrupt load configura tion dut int ack from slave ack from slave 1.5 v
PCA9554A scps127e ? september 2006 ? revised june 2014 www.ti.com parameter measurement information (continued) a. c l includes probe and jig capacitance. b. t pv is measured from 0.7 v cc on scl to 50% i/o pin output. c. all inputs are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 ? , t r /t f 30 ns. d. the outputs are measured one at a time, with one transition per measurement. e. all parameters and waveforms are not applicable to all devices. figure 16. p-port load circuit and voltage waveforms 12 submit documentation feedback copyright ? 2006 ? 2014, texas instruments incorporated product folder links: PCA9554A p0 a 0.7 v cc 0.3 v cc scl p7 ??? ??? ??? ??? t pv (see note b) slave ack unstable data last stable bit sda p n p n write mode (r/w = 0) p0 a 0.7 v cc 0.3 v cc scl p7 0.7 v cc 0.3 v cc t ps t ph read mode (r/w = 1) p-port load configura tion dut c l = 50 pf (see note a) pn 2 v cc 500 500 1.5 v
PCA9554A www.ti.com scps127e ? september 2006 ? revised june 2014 8 detailed description 8.1 functional block diagram a. pin numbers shown are for the db, dbq, dgv, dw, or pw package. b. all i/os are set to inputs at reset. figure 17. logic diagram copyright ? 2006 ? 2014, texas instruments incorporated submit documentation feedback 13 product folder links: PCA9554A 14 i/o port shift register 8 bits lp filter interrupt logic inputfilter 15 power-on reset read pulse w rite pulse 2 1 1316 8 gnd v cc sda scl a1 a0 int i 2 c bus control p7?p0 3 a2
PCA9554A scps127e ? september 2006 ? revised june 2014 www.ti.com functional block diagram (continued) a. at power-on reset, all registers return to default values. figure 18. simplified schematic of p0 to p7 8.2 device functional modes 8.2.1 power-on reset when power (from 0 v) is applied to v cc , an internal power-on reset holds the PCA9554A in a reset condition until v cc has reached v por . at that point, the reset condition is released and the PCA9554A registers and i 2 c/smbus state machine will initialize to their default states. after that, v cc must be lowered to below 0.2 v and then back up to the operating voltage for a power-reset cycle. refer to the power-on reset errata section. 8.2.2 i/o port when an i/o is configured as an input, fets q1 and q2 (in figure 18 ) are off, which creates a high impedance input with a weak pullup (100 k ? typ) to v cc . the input voltage may be raised above v cc to a maximum of 5.5 v. if the i/o is configured as an output, q1 or q2 is enabled, depending on the state of the output port register. in this case, there are low impedance paths between the i/o pin and either v cc or gnd. the external voltage applied to this i/o pin should not exceed the recommended levels for proper operation. 8.2.3 interrupt output ( int) an interrupt is generated by any rising or falling edge of the port inputs in the input mode. after time, t iv , the signal int is valid. resetting the interrupt circuit is achieved when data on the port is changed to the original setting, data is read from the port that generated the interrupt. resetting occurs in the read mode at the acknowledge (ack) or not acknowledge (nack) bit after the rising edge of the scl signal. 14 submit documentation feedback copyright ? 2006 ? 2014, texas instruments incorporated product folder links: PCA9554A data from shift register data from shift register w rite configuration pulse w rite pulse read pulse w rite polarity pulse data from shift register output port register configuration register input port register polarity inversion register polarityregister data input portregister data gnd p0 to p7 v cc output portregister data q1 q2 dc k ff qq dc k ff qq dc k ff qq dc k ff qq int 100 k
PCA9554A www.ti.com scps127e ? september 2006 ? revised june 2014 device functional modes (continued) interrupts that occur during the ack or nack clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. each change of the i/os after resetting is detected and is transmitted as int. writing to another device does not affect the interrupt circuit, and a pin configured as an output cannot cause an interrupt. changing an i/o from an output to an input may cause a false interrupt to occur, if the state of the pin does not match the contents of the input port register. because each 8-pin port is read independently, the interrupt caused by port 0 is not cleared by a read of port 1 or vice versa. the int output has an open-drain structure and requires pull-up resistor to v cc . 8.2.3.1 interrupt errata description the int will be improperly de-asserted if the following two conditions occur: 1. the last i 2 c command byte (register pointer) written to the device was 00h. note this generally means the last operation with the device was a read of the input register. however, the command byte may have been written with 00h without ever going on to read the input register. after reading from the device, if no other command byte written, it will remain 00h. 2. any other slave device on the i 2 c bus acknowledges an address byte with the r/w bit set high system impact can cause improper interrupt handling as the master will see the interrupt as being cleared. system workaround minor software change: user must change command byte to something besides 00h after a read operation to the PCA9554A device or before reading from another slave device. note software change will be compatible with other versions (competition and ti redesigns) of this device. 8.3 programming 8.3.1 i 2 c interface the bidirectional i 2 c bus consists of the serial clock (scl) and serial data (sda) lines. both lines must be connected to a positive supply through a pullup resistor when connected to the output stages of a device. data transfer may be initiated only when the bus is not busy. i 2 c communication with this device is initiated by a master sending a start condition, a high-to-low transition on the sda input/output while the scl input is high (see figure 19 ). after the start condition, the device address byte is sent, most significant bit (msb) first, including the data direction bit (r/ w). after receiving the valid address byte, this device responds with an acknowledge (ack), a low on the sda input/output during the high of the ack-related clock pulse. the address inputs (a0 ? a2) of the slave device must not be changed between the start and stop conditions. on the i 2 c bus, only one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control commands (start or stop) (see figure 20 ). a stop condition, a low-to-high transition on the sda input/output while the scl input is high, is sent by the master (see figure 19 ). copyright ? 2006 ? 2014, texas instruments incorporated submit documentation feedback 15 product folder links: PCA9554A
PCA9554A scps127e ? september 2006 ? revised june 2014 www.ti.com programming (continued) any number of data bytes can be transferred from the transmitter to receiver between the start and stop conditions. each byte of eight bits is followed by one ack bit. the transmitter must release the sda line before the receiver can send an ack bit. the device that acknowledges must pull down the sda line during the ack clock pulse so that the sda line is stable low during the high pulse of the ack-related clock period (see figure 21 ). when a slave receiver is addressed, it must generate an ack after each byte is received. similarly, the master must generate an ack after each byte that it receives from the slave transmitter. setup and hold times must be met to ensure proper operation. a master receiver will signal an end of data to the slave transmitter by not generating an acknowledge (nack) after the last byte has been clocked out of the slave. this is done by the master receiver by holding the sda line high. in this event, the transmitter must release the data line to enable the master to generate a stop condition. figure 19. definition of start and stop conditions figure 20. bit transfer figure 21. acknowledgment on the i 2 c bus 16 submit documentation feedback copyright ? 2006 ? 2014, texas instruments incorporated product folder links: PCA9554A data output by t ransmitter scl from master start condition s 1 2 8 9 data output by receiver clock pulse for acknowledgment nack ack sda scl data line stable; data v alid change of data allowed sda scl start condition s stop condition p
PCA9554A www.ti.com scps127e ? september 2006 ? revised june 2014 programming (continued) 8.3.2 register map table 1. interface definition bit byte 7 (msb) 6 5 4 3 2 1 0 (lsb) i 2 c slave address l h h h a2 a1 a0 r/ w px i/o data bus p7 p6 p5 p4 p3 p2 p1 p0 8.3.2.1 device address figure 22 shows the address byte for the PCA9554A. figure 22. PCA9554A address table 2. address reference inputs i 2 c bus slave address a2 a1 a0 l l l 56 (decimal), 38 (hexadecimal) l l h 57 (decimal), 39 (hexadecimal) l h l 58 (decimal), 3a (hexadecimal) l h h 59 (decimal), 3b (hexadecimal) h l l 60 (decimal), 3c (hexadecimal) h l h 61 (decimal), 3d (hexadecimal) h h l 62 (decimal), 3e (hexadecimal) h h h 63 (decimal), 3f (hexadecimal) the last bit of the slave address defines the operation (read or write) to be performed. when it is high (1), a read is selected. a low (0) selects a write operation. 8.3.2.2 control register and command byte following the successful acknowledgment of the address byte, the bus master sends a command byte that is stored in the control register in the PCA9554A. two bits of this command byte state the operation (read or write) and the internal register (input, output, polarity inversion or configuration) that will be affected. this register can be written or read through the i 2 c bus. the command byte is sent only during a write transmission. once a command byte has been sent, the register that was addressed continues to be accessed by reads until a new command byte has been sent. figure 23. control register bits copyright ? 2006 ? 2014, texas instruments incorporated submit documentation feedback 17 product folder links: PCA9554A 0 0 0 0 b1 b0 0 0 0 1 1 1 a1 a2 a0 slave address r/w fixed hardware selectable
PCA9554A scps127e ? september 2006 ? revised june 2014 www.ti.com table 3. command byte control register bits command byte power-up register protocol (hex) default b1 b0 0 0 0x00 input port read byte xxxx xxxx 0 1 0x01 output port read/write byte 1111 1111 1 0 0x02 polarity inversion read/write byte 0000 0000 1 1 0x03 configuration read/write byte 1111 1111 8.3.2.3 register descriptions the input port register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the configuration register. it only acts on read operation. writes to these registers have no effect. the default value, x, is determined by the externally applied logic level. before a read operation, a write transmission is sent with the command byte to let the i 2 c device know that the input port register will be accessed next. table 4. register 0 (input port register) bit i7 i6 i5 i4 i3 i2 i1 i0 default x x x x x x x x the output port register (register 1) shows the outgoing logic levels of the pins defined as outputs by the configuration register. bit values in this register have no effect on pins defined as inputs. in turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value. table 5. register 1 (output port register) bit o7 o6 o5 o4 o3 o2 o1 o0 default 1 1 1 1 1 1 1 1 the polarity inversion register (register 2) allows polarity inversion of pins defined as inputs by the configuration register. if a bit in this register is set (written with 1), the corresponding port pin polarity is inverted. if a bit in this register is cleared (written with a 0), the corresponding port pin original polarity is retained. table 6. register 2 (polarity inversion register) bit n7 n6 n5 n4 n3 n2 n1 n0 default 0 0 0 0 0 0 0 0 the configuration register (register 3) configures the directions of the i/o pins. if a bit in this register is set to 1, the corresponding port pin is enabled as an input with high impedance output driver. if a bit in this register is cleared to 0, the corresponding port pin is enabled as an output. table 7. register 3 (configuration register) bit c7 c6 c5 c4 c3 c2 c1 c0 default 1 1 1 1 1 1 1 1 8.3.2.4 bus transactions data is exchanged between the master and PCA9554A through write and read commands. 18 submit documentation feedback copyright ? 2006 ? 2014, texas instruments incorporated product folder links: PCA9554A
PCA9554A www.ti.com scps127e ? september 2006 ? revised june 2014 8.3.2.4.1 writes data is transmitted to the PCA9554A by sending the device address and setting the least-significant bit to a logic 0 (see figure 22 for device address). the command byte is sent after the address and determines which register receives the data that follows the command byte (see figure 24 and figure 25 ). there is no limitation on the number of data bytes sent in one write transmission. figure 24. write to output port register < br/ > figure 25. write to configuration or polarity inversion registers copyright ? 2006 ? 2014, texas instruments incorporated submit documentation feedback 19 product folder links: PCA9554A scl sda data to register start condition r/w ack from slave ack from slave ack from slave 1 9 8 7 6 5 4 3 2 data 1/0 a2 0 1 s 1 1 a1 a0 0 a 1 0 0 0 0 0 0 a a p data to register command byte slave address scl start condition data 1 v alid sda w rite to port data out from port r/w ack from slave ack from slave ack from slave 1 9 8 7 6 5 4 3 2 data 1 1 a2 0 1 s 1 1 a1 a0 0 a 0 0 0 0 0 0 0 a a p t pv data to port command byte slave address
PCA9554A scps127e ? september 2006 ? revised june 2014 www.ti.com 8.3.2.4.2 reads the bus master first must send the PCA9554A address with the least significant bit (lsb) set to a logic 0 (see figure 22 for device address). the command byte is sent after the address and determines which register is accessed. after a restart, the device address is sent again, but this time the lsb is set to a logic 1. data from the register defined by the command byte then is sent by the PCA9554A (see figure 26 and figure 27 ). after a restart, the value of the register defined by the command byte matches the register being accessed when the restart occurred. data is clocked into the register on the rising edge of the ack clock pulse. there is no limitation on the number of data bytes received in one read transmission, but when the final byte is received, the bus master must not acknowledge the data. figure 26. read from register < br/ > a. this figure assumes the command byte has previously been programmed with 00h. b. transfer of data can be stopped at any moment by a stop condition. c. this figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address call and actual data transfer from the p port. see figure 26 for these details. figure 27. read from input port register 20 submit documentation feedback copyright ? 2006 ? 2014, texas instruments incorporated product folder links: PCA9554A a2 0 1 s 1 1 a1 a0 0 a a data from register slave address slave address r/w ack from slave command byte ack from slave s a2 0 1 1 1 a1 a0 r/w 1 a data a ack from master data data from register nack from master na p last byte ack from slave scl sda int start condition r/w read from port data into port stopcondition ack from master nack from master ack from slave data from port slave address data from port 1 9 8 7 6 5 4 3 2 a2 0 1 s 1 1 a1 a0 1 a data 1 data 4 a na p data 2 data 3 data 4 t iv t ph t ps t ir data 5
PCA9554A www.ti.com scps127e ? september 2006 ? revised june 2014 9 application and implementation 9.1 typical application figure 28 shows an application in which the PCA9554A can be used. a. device address is configured as 0111000 for this example. b. p0, p2, and p3 are configured as outputs. c. p1, p4, and p5 are configured as inputs. d. p6 and p7 are not used and have internal 100-k ? pullup resistors to protect them from floating. figure 28. typical application copyright ? 2006 ? 2014, texas instruments incorporated submit documentation feedback 21 product folder links: PCA9554A a2a1 sda scl int gnd p6 p0p1 p2 p3 p4 p5 p7 int gnd v cc v cc (5 v) v cc 10 k 10 k 10 k 2 k mastercontroller PCA9554A int reset subsystem 2 (e.g., counter) subsystem 3 (e.g., alarm system) alarm controlled device(e.g., cbt device) enable a b v cc subsystem 1 (e.g., t emperature sensor) sdascl a0
PCA9554A scps127e ? september 2006 ? revised june 2014 www.ti.com typical application (continued) 9.1.1 detailed design procedure 9.1.1.1 minimizing i cc when i/os control leds when the i/os are used to control leds, they are normally connected to v cc through a resistor as shown in figure 28 . because the led acts as a diode, when the led is off, the i/o v in is about 1.2 v less than v cc . the supply current, i cc , increases as v in becomes lower than v cc and is specified as i cc in electrical characteristics . for battery-powered applications, it is essential that the voltage of i/o pins is greater than or equal to v cc when the led is off to minimize current consumption. figure 29 shows a high-value resistor in parallel with the led. figure 30 shows v cc less than the led supply voltage by at least 1.2 v. both of these methods maintain the i/o v in at or above v cc and prevents additional supply-current consumption when the led is off. figure 29. high-value resistor in parallel with the led figure 30. device supplied by a lower voltage 22 submit documentation feedback copyright ? 2006 ? 2014, texas instruments incorporated product folder links: PCA9554A led 3.3 v 5 v ledx v cc led ledx v cc 100 k v cc
PCA9554A www.ti.com scps127e ? september 2006 ? revised june 2014 10 power supply recommendations 10.1 power-on reset errata a power-on reset condition can be missed if the vcc ramps are outside specification listed below. system impact if ramp conditions are outside timing allowances above, por condition can be missed, causing the device to lock up. 11 device and documentation support 11.1 trademarks all trademarks are the property of their respective owners. 11.2 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 11.3 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 12 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. copyright ? 2006 ? 2014, texas instruments incorporated submit documentation feedback 23 product folder links: PCA9554A
package option addendum www.ti.com 24-apr-2015 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples PCA9554Adb active ssop db 16 80 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 pd554a PCA9554Adbqr nrnd ssop dbq 16 tbd call ti call ti -40 to 85 PCA9554Adbr active ssop db 16 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 pd554a PCA9554Adgv nrnd tvsop dgv 16 tbd call ti call ti -40 to 85 PCA9554Adgvr active tvsop dgv 16 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 pd554a PCA9554Adgvrg4 active tvsop dgv 16 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 pd554a PCA9554Adw active soic dw 16 40 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 PCA9554A PCA9554Adwr active soic dw 16 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 PCA9554A PCA9554Adwrg4 active soic dw 16 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 PCA9554A PCA9554Apw nrnd tssop pw 16 90 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 pd554a PCA9554Apwg4 nrnd tssop pw 16 90 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 pd554a PCA9554Apwr nrnd tssop pw 16 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 pd554a PCA9554Apwrg4 nrnd tssop pw 16 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 pd554a PCA9554Argtr active qfn rgt 16 3000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 zvh PCA9554Argvr active vqfn rgv 16 2500 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 pd554a (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device.
package option addendum www.ti.com 24-apr-2015 addendum-page 2 (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant PCA9554Adbr ssop db 16 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 q1 PCA9554Adgvr tvsop dgv 16 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 q1 PCA9554Adwr soic dw 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 q1 PCA9554Apwr tssop pw 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 q1 PCA9554Argtr qfn rgt 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 q2 PCA9554Argvr vqfn rgv 16 2500 330.0 12.4 4.25 4.25 1.15 8.0 12.0 q2 package materials information www.ti.com 14-jul-2012 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) PCA9554Adbr ssop db 16 2000 367.0 367.0 38.0 PCA9554Adgvr tvsop dgv 16 2000 367.0 367.0 35.0 PCA9554Adwr soic dw 16 2000 367.0 367.0 38.0 PCA9554Apwr tssop pw 16 2000 367.0 367.0 35.0 PCA9554Argtr qfn rgt 16 3000 367.0 367.0 35.0 PCA9554Argvr vqfn rgv 16 2500 367.0 367.0 35.0 package materials information www.ti.com 14-jul-2012 pack materials-page 2

mechanical data msso002e ? january 1995 ? revised december 2001 post office box 655303 ? dallas, texas 75265 db (r-pdso-g**) plastic small-outline 4040065 /e 12/01 28 pins shown gage plane 8,20 7,40 0,55 0,95 0,25 38 12,90 12,30 28 10,50 24 8,50 seating plane 9,90 7,90 30 10,50 9,90 0,38 5,60 5,00 15 0,22 14 a 28 1 20 16 6,50 6,50 14 0,05 min 5,90 5,90 dim a max a min pins ** 2,00 max 6,90 7,50 0,65 m 0,15 0 ? 8 0,10 0,09 0,25 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0,15. d. falls within jedec mo-150

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